Low-power inverter for crystal oscillator buffer or the like
US5457433A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1993 |
| Grant date | Oct 10, 1995 |
| Priority date | — |
| Expiry date | Aug 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B2202/042
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.