Memory system for use in a moving image decoding processor employing motion compensation technique
US5457481A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1993 |
| Grant date | Oct 10, 1995 |
| Priority date | — |
| Expiry date | Oct 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/20052
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus for use in a receiver for decoding video signals comprises a first memory for storing an image frame; a second memory for storing current pixel data temporally and providing the same to said first memory; an address generator for generating address signals for sequentially addressing two-dimensional pixels in the blocks; a delay unit for delaying said address signals by a predetermined delay time in generating write address signals for said first memory; an offset unit for comparing the said address signals with an offset address so as to prohibit the provision of write address signals to said first memory until one of said address signals reaches to said offset address; and a control circuit for selectively providing the read address signals and the write address signals to said first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.