Test circuit having a plurality of scan latch circuits
US5457698A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1993 |
| Grant date | Oct 10, 1995 |
| Priority date | — |
| Expiry date | Jan 25, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A technique for reducing the circuit area of a test circuit which is formed by a parallel register which includes a plurality of scan latch circuits is disclosed. A scan latch circuit is formed by a master-slave latch circuit. The master-slave latch circuit includes a static latch circuit which serves as a master side latch circuit and a dynamic latch circuit which serves as a slave side latch circuit. Under the control of a control signal, either a signal inputted to a first circuit part or a signal inputted to a preceding stage scan latch circuit is held in the static latch circuit. The signal which was inputted to a first circuit part is outputted via an output terminal of the scan latch circuit to a second circuit part. The signal which was inputted to the preceding stage scan latch circuit is advanced to the dynamic latch circuit and thereafter outputted to a next scan latch circuit via other output terminal of the scan latch circuit. Thus, since the dynamic latch circuit is used as the slave since latch circuit, the test circuit includes less elements, thereby less circuit area is required for the test circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.