Method for forming wiring pattern
US5458763A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1993 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Nov 12, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1492
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A wiring pattern forming method in which side etch of a wiring pattern at the time of etching the substrate copper foil of a copper plating pattern is reduced to hold down an increase in line resistance, the wiring pattern forming method including the steps of: providing a plating resist pattern of which open area comprises a wiring pattern on the surface of a copper-clad laminate which is obtained by providing a copper foil on an insulating substrate; plating such open area with copper to form a copper plating pattern; then plating a crevice between the copper plating pattern and the plating resist pattern with a solder film by alternately repeating application of a current for a predetermined time period and suspension of the current application for a predetermined time period; and etching away the copper foil by using the solder film as an etching resist to form the wiring pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.