Video images decoder architecture for implementing a 40 MS processing algorithm in high definition television
US5459519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1994 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | May 11, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/0155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (J,L), which comprises a video signal demultiplexer receiving the transmission channels (J,L); and respective processing blocks for separately handling the signals from each of the channels (J,L). Each processing block includes a video image format converter, a local memory connected to an output of the converter, and at least one median filter and one systolic filter cascade connected after the memory for restoring, by interpolation, signal samples related to successive lines of the video image. A summing node adds the outputs from each processing block so as to obtain a time mean between restored samples of the channels (J,L). This architecture drastically reduces the number of memories required for processing the restored algorithm, as well as reducing overall silicon area requirements for the system. Accordingly, the whole 40-millisecond processing portion may be integrated into a single chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.