Method and apparatus for optimizing electronic circuits
US5459673A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1994 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Apr 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for sizing components of an electronic circuit by replacing standard cells representative of the components in the circuit with other standard cells from a standard cell library in order to improve the performance so that the circuit meets certain predetermined user-specified criteria. A computer program implementation ("the sizing system") of this method is described. This implementation receives command line options from the user, builds an internal representation of the external standard cell library, builds a database describing the connectivity of the circuit, computes the capacitance seen at each node in the circuit, and queries the user for additional command options. One such option is for the sizing system to size the circuit, via a heuristic algorithm, by replacing standard cells in the circuit with others from a standard cell library in order to improve the circuit's performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.