Multiple level random access memory
US5459686A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1993 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Oct 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to the present invention comprises a number of memory cells that store multiple voltage levels. Each voltage level is uniquely assigned to a different logic level. Multiple binary codes are converted to various analog voltage levels by a digital to analog converter. The memory cell of the invention comprises a storage capacitor and transfer gates, each terminal of which is connected to a bit line through the transfer gate for isolating the storage capacitor from the interference of other circuits while it is not accessed. In the writing cycle, analog voltage can be stored in the storage capacitor of each cell by applying the assigned analog voltage generated by the digital to analog converter through, bit lines and the transfer gates that control the conductivity between the bit lines and storage capacitor. In the reading cycle, a stored voltage can be applied to a digital to analog converter by making the transfer gates conductive between the storage capacitor and the bit lines. The invention further comprises a set of transfer gates, which comprises a pair of complementary types of transistors such as n-channel CMOS FET and p-channel CMOS F…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.