Integrated semiconductor memory with redundancy arrangement

US5459690A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Johann Rieger · Monsheim, DE
• Johann Stecker · Hersbruck, DE

Key dates

• Filing date: Aug 17, 1992
• Grant date: Oct 17, 1995
• Expiry date: Aug 17, 2012

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/846
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated semiconductor memory has a block decoder BKDEC having block selection signals BKS and a plurality of main memory area block units BK which can be individually activated. The main memory area block units BK contain memory locations which can be selected via word and bit lines NWL, NBL, NBL and redundancy memory locations RMC, which can be selected via redundancy word lines RWL. The main memory area block units BK contain programmable redundancy block decoders RBK, which in conjunction with redundancy word line decoders RWDEC enable the selection of redundancy word lines RWL. If a redundancy word line RWL is to be selected, it is exclusively that main memory area block unit BK in which the redundancy word line RWL that is to be selected is contained that is activated. In this case, activation which is otherwise usual is suppressed via an appropriate block selection signal BKS. It is rendered possible in this way that the redundancy word line RWL that is to be selected together with its redundancy memory locations RMC can be arranged in a different main memory area block unit BK from the memory locations to be replaced together with their normal word lines NWL, but also …