Memory circuit
US5459691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1994 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Sep 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit, in which test data are compared with stored data, comprises a plurality of memory cells each having two complementary data outputs indicative of a respective stored bit of the stored data. The two complementary outputs are selectively interchanged, in response to a respective test bit of the test data. An output signal is then generated (e.g. by a sense amplifier) in response to the relative polarities of the two complementary data outputs. The output signal is indicative of whether the stored bit is equal to the test bit. Where a multi-bit word is stored in a plurality of the memory cells, the output signals generated by a comparison of each stored bit of the multi-bit word and respective bits of the test data are combined by, for example, an AND gate. The output of the AND gate indicates whether the test data matches the stored multi-bit word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.