Link error monitoring
US5459731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1993 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Jun 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/106
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a communication network, an efficient link error monitor is provided that completely relieves the microprocessor of computing the link error rate and comparing it with link error rate thresholds. The link error rate computation and the comparison are performed by the physical layer of a communication station. The physical layer generates an interrupt to the microprocessor only if a threshold is crossed and a microprocessor action may be required. The physical layer includes a number of registers that can be conveniently written by the microprocessor to designate the thresholds and monitor the link errors. The link error rate is estimated using a simple estimator that provides a realistic link error rate estimate even at early stages of operation when few link errors have been detected and when, therefore, little statistical information on the link error rate exists.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.