Simple digital method for controlling digital signals to achieve synchronization
US5459752A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1993 |
| Grant date | Oct 17, 1995 |
| Priority date | — |
| Expiry date | Nov 17, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A simple digital method is disclosed for controlling the digital signals sent out from a pluralities of identical signal processors (i.e, signal generators) so as to achieve synchronization. The method comprises the steps of: (a) obtaining a gate array logic circuit containing a plurality of pairs of comparison terminals and reference terminals, each of the comparison terminals is connected to a respective signal processor and the reference terminals are respectively connected to at least two different signal processors; (b) performing a gate array logic circuit operation, which comprises the following sub-steps: (i) performing a waiting procedure for each pair of comparison terminal and reference terminal until it is received that the comparison terminal is "1" and the reference terminal is "0", then moving to a gate procedure; otherwise, continuing the waiting procedure (i.e., no disable signal is sent out); (ii) performing a gate procedure by continuously sending out a "1" gate signal, i.e., the gate being set at "1" state (i.e., disable signal), until a "1" signal is received at the reference terminal is "1", then moving to a reset procedure; (c) performing a reset procedure by…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.