RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder

US5459843A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gordon Taylor Davis · Boca Raton, US
• Sebastian T. Ventrone · South Burlington, US
• John J. Reilly · Burlington, US
• Baiju D. Mandalia · Boca Raton, US
• Michael G. Holung · Boca Raton, US
• William R. Robinson, Jr. · West Palm Beach, US

Key dates

• Filing date: Jul 28, 1994
• Grant date: Oct 17, 1995
• Expiry date: Jul 28, 2014

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3851
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.