Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing
US5461333A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-chip module is composed of two or more integrated-circuit chips located on a substrate such as a dielectrically coated silicon substrate. The chips are interconnected by means of transmission wiring lines. At least some of the chips contain one or more input buffer circuits, each composed of two branches ("legs"). Each such branch contains, in one embodiment, an n-channel MOS transistor connected in series with a pair of series-connected p-channel MOS transistors--whereby, in each such branch, one of the p-channel MOS transistors is located between (intermediate) the other of the p-channel MOS transistors and the n-channel MOS transistor of that same branch. On the other hand, in each buffer circuit, the intermediate p-channel MOS transistors of both branches are cross-coupled. Each of the n-channel MOS transistors is connected in a common gate configuration to receive one of the complementary input signals coming from the transmission wiring lines, and the other of the p-channel transistors in each branch is connected in a common source configuration to receive the other of the complementary input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.