Decimation filter for a sigma-delta converter and A/D converter using the same
US5461641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1992 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Nov 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.