System and method for peripheral data transfer
US5461701A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1992 |
| Grant date | Oct 24, 1995 |
| Priority date | — |
| Expiry date | Dec 18, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for increasing the rate of data transfer from a host computer to a peripheral without the need for special hardware within the host computer or a special interface cable coupling the host computer to the peripheral. Some simple hardware modifications are required within the peripheral interface. Data is transferred from the host computer to the peripheral in 4 KByte bursts. Handshaking occurs between the host computer and the peripheral only between bursts. Each byte of peripheral data is apportioned into two nibbles within the host computer. Two bytes are transmitted from the host computer to the peripheral, each transmitted byte containing two data clocks, a panty bit, and a nibble of peripheral data. Within the peripheral, a clock circuit receives the two clock signals from each transmitted byte and generates delayed signals to latch the nibbles of peripheral data into storage registers. The latching signals are generated only after the logic transition of both clock signals. The storage registers are used to reform the original byte of peripheral data from the two nibbles. In addition, one of the transmitted bytes contains a flag to signal the peripheral tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.