Control unit for the common memory of an ATM node
US5463622A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1991 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Oct 9, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5636
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for controlling the common memory of an ATM-node. The nodes serve for the continuous reception and onward routing of address-labelled cells with uniform length and uniform construction. The apparatus includes means for management and control and a sequencer for managing the storage blocks of the common memory and for controlling the sequential reading in and reading out of cells, respectively, into or out of said storage blocks. The circuits for management and control include at least one addressable read/write store, a monitor logic, an input logic, a bus- and control-logic, and a comparator, the read/write store includes a number of storage locations equal to the third plurality plus two times the second plurality multiplied by the quantity, plus 2. Every storage location of the read/write store is constructed for storing an address. Two times the second plurality of the storage locations multiplied by the quantity is associated in pairs with the outgoing lines, and the third plurality of storage locations is associated with the storage blocks of the common memory. Two of the storage locations are associated with the empty storage blocks of the common memo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.