Single-ended pulse gating circuit
US5463655A · kind A · utility
9Cited by
10References
78Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 17, 1993 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Feb 17, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0807
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a gating circuit having two separate paths for detecting even and odd bits. Each path includes an equal number of coupled flip-flops. After bit detection, combinational logic merges the two paths to provide an output signal. An optional reset signal initializes all flip-flops to a logic zero at the start of a data read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.