Emulation of slower speed processor
US5463744A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1994 |
| Grant date | Oct 31, 1995 |
| Priority date | — |
| Expiry date | Mar 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse width modulation circuit in a computer system for emulating a processor operating at a slower instruction execution speed. The pulse width modulator a computer system clock, and a register containing a first value. The first value is user-definable by software and specifies a proportion of time that a processor should remain idle. The apparatus further comprises a counter coupled to the clock, the counter having a range between a second and third values which includes the first value. A comparator is coupled to the counter and the register, and the comparator causes a central processing unit to suspend instruction execution for a specified interval of time. The comparator causes the central processing unit to resume instruction execution for remainder of the counter's range. The processor is therefore kept idle for proportions of time depending on the values of the register and the counter to emulate a slower speed processor. For high performance processors which have an on processor cache, the cache is flushed and disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.