High frequency transistor with reduced parasitic inductance
US5465007A · kind A · utility
5Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1994 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Jul 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a transistor mounted on the top surface of a substrate. A metal sheet is disposed on a metallized electrode on the substrate to which the emitter, for example, of the transistor is electrically connected. The emitter is electrically connected by a thin metal wire to the metal sheet. An MOS capacitor is disposed on the metal sheet, and a plated through-hole beneath the metal sheet connects the metallized electrode directly to a metallized ground electrode disposed on the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.