High voltage CMOS logic using low voltage CMOS process
US5465054A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1994 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Apr 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices. The source-drain channel of a p-channel output shielding transistor couples the output port of p-channel switching transistors to the gate output; the gate terminal of the such p-channel output shielding transistor is coupled to the shield voltage for preventing the drain of p-channel switching transistors from being pulled down below the shield voltage. A similar n-channel output shielding transistor couples the output port of n-channel switching transistor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.