Three input arithmetic logic unit forming the sum of a first Boolean combination of first, second and third inputs plus a second Boolean combination of first, second and third inputs
US5465224A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1993 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Nov 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.