Shared memory array for data block and control program storage in disk drive
US5465343A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved disk drive architecture includes a microcontroller interface circuit connected between a drive microcontroller and a buffer controller. The microcontroller interface circuit includes address mapping registers for mapping at least one predetermined portion of directly addressable memory of the microcontroller to address locations of the drive's cache buffer. The buffer controller circuit includes an access arbitration circuit for arbitrating requests for access to the cache buffer by the drive's data sequencer, the drive's host interface controller and the drive's microcontroller. A microcontroller wait state generator responds to the access arbitration circuit by generating and applying a wait state sequence to the microcontroller until a request it makes for access to the cache buffer can be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.