Parallel processing of received and transmitted bit stream in telecommunications equipment including a DSP and supporting HDLC/SDLC protocols
US5465345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1992 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Sep 21, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Parallel processing method in a telecommunication equipment including a Digital Signal Processing system (202) associated with some RAM storage. The telecommunication equipment receives bit streams transporting HDLC/SDLC frames. For receiving bit streams the method involves the steps of building at least one table providing the `0` deletion and character alignment functions required in the HDLC/SDLC management procedures, receiving the incoming bit stream and assembling samples of n consecutive bits therefrom to be processed in parallel, and using said assembled n consecutive bits as addressing elements for accessing said at least one table in order to derive a character corresponding to data to be extracted from the HDLC frame. For transmitting bit streams, the method elaborates the transmitted HDLC bit streams by building at least one table (5, 45, 48) providing the `0` insert and character alignment functions required in the HDLC/SDLC management procedures, extracting the characters to transmit to the HDLC line and assembling n consecutive bits therefrom to be processed in parallel, and using said assembled n consecutive bits as addressing elements for accessing said at least on…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.