Multiprocessor system with cascaded modules combining processors through a programmable logic cell array
US5465375A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1993 |
| Grant date | Nov 7, 1995 |
| Priority date | — |
| Expiry date | Jan 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V30/424
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a specialized processing unit such as a digital signal processor (DSP). A first interface, the first memory and the data processing unit are interconnected by a module bus. A fourth interface, the second memory and the specialized processing unit are interconnected by another module bus. A feedback bus connects the second and third interfaces in the last and first modules for constituting a ring. Such a system is particularly intended for image recognition, such as digitalized handwritten digits for postal distribution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.