Quick resolving latch
US5467038A · kind A · utility
118Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Feb 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.