Method for adjusting clock skew
US5467040A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1993 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Jul 28, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.