Variable delay buffer circuit
US5467041A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Jun 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay buffer circuit composed of a cascade of variable delay buffers, which realizes a delay in response to a delay control signal without any glitches. The delay buffers each have a selector circuit for selecting one of an input signal and a delayed signal produced by delaying in time the input signal in response to a delaying information. The delay buffers each contains a first control means and an output means. The first control means controls a timing of a input of the delaying information into the selector circuit in response to an external control signal. The output means outputs the control signal to by synchronized with an output signal from the selector circuit. Preferably, the first control means contains a latching means for latching the delay information and a second control means for controlling a timing in output of the delay information from the latching means in response to the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.