Low power clocking apparatus and method
US5467042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1993 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Nov 8, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.