Integrator including an offset eliminating circuit and capable of operating with low voltage
US5467045A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Oct 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/186
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A complete type integrator is disclosed which is designed such that the time-constant thereof can be controlled; wide input and output dynamic ranges can be achieved; operation with low power supply voltage is possible; and no offset voltage is generated. More specifically, the integrator comprises an amplifier circuit having a combination of a first and a second differential amplifier circuit (A1, A2) and connected to the input side of an integrator circuit; and an offset eliminating circuit connected to that portion of the amplifier circuit where the input signal (9) is applied. The offset eliminating circuit comprises a combination of a first, a second and a third current-mirror circuit (B1, B2, B3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.