Dynamic biasing circuit for semiconductor device
US5467050A · kind A · utility
17Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Jan 4, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.