M&A for minimizing data transfer to main memory from a writeback cache during a cache miss
US5467460A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 1994 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Apr 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory having at least two modified bits for each block of data coupled to a WriteBack buffer circuit is described for transferring a fraction of the data block when a cache miss occurs. In the preferred embodiment of the present invention, the data array of the data cache is partitioned into two halves, each block of data has two modified bits. When a cache miss occurs, a replacement algorithm determines which of the lines in a given set shall be replaced. The contents of the chosen line in the data cache is written, copied to a WriteBack buffer circuit. The line of data from external memory is then written into the data cache, clearing the two modified bits in the data cache in the process. If only one modified bit is set, only half of a block of data is written back into the data cache. Thus, the present invention minimizes the data transfer from a data cache during a cache miss by transferring only half a block of data when the required data from the external memory is less than half of a block of data in length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.