Out of order instruction load and store comparison
US5467473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1993 |
| Grant date | Nov 14, 1995 |
| Priority date | — |
| Expiry date | Jan 8, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system allows for out of order instruction execution and includes at least one load/store unit for loading instructions to a register for processing by a fixed point unit, floating point unit, or the like, and store the results to memory. A load queue maintains the addresses and program numbers of the load instructions. During execution the address of the store instruction is compared to the address in the load queue of previously executed load instructions. A program counter compares the program number of the store instruction with the program number of the load instruction in the load queue. If the addresses are different, then no impermissible out of order situation exists between the load and store instructions being compared, because the data is not at the same address. If the address is the same, and the store program number is greater than the load program number, then the instructions have been executed in order (the load correctly preceded the store) and no problem exists. However, if the addresses are the same and the load instruction has been incorrectly reordered to precede the store instruction, then a reordering conflict exists and the load instructions m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.