Method for forming low and high minority carrier lifetime layers in a single semiconductor structure
US5468674A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Jun 8, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.