Flip-flop for use in LSSD gate arrays
US5469079A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Sep 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop designed for use in gate arrays following LSSD design rules. The flip-flop has a data input D and a scan data input SD which are gated by control signals fmc, fmc' to the flip-flop input terminal 18. The flip-flop input 18 is gated into a master flip-flop consisting of two inverters 30, 32 coupled back-to-back by a gate signal DMC which is valid when the desired input signal is gated to the flip-flop input 18. The master flip-flop is coupled to a slave flip-flop which is gated by a different control signal. The slave flip-flop consists of two inverters 44, 46 coupled back-to-back. Inverters 48, 50 coupled to the slave flip-flop provide a buffered output therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.