Shared line buffer architecture for a video processing circuit
US5469223A · kind A · utility
104Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Mar 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A single line buffer in a motion video card is used for both vertical reduction of the pixel image before storage in a video memory buffer and vertical expansion of the pixel image after being outputted by the video memory buffer. When the desired display size is smaller than the original pixel image size, then the line buffer is used by the input pipeline to reduce the image. When the desired display size is larger than the original pixel image size (or larger than the image stored in the memory buffer), then the line buffer is used by the output pipeline to enlarge the image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.