Content addressable memory having match line transistors connected in series and coupled to current sensing circuit
US5469378A · kind A · utility
19Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Apr 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a contents addressable memory for a fully associative cache memory in which address bit values in respect of data to be retrieved from cache are applied to the bit lines of respective columns of cells for comparison with the bit values held by the cells, a match in any one cell is arranged to forward bias a match line device in that cell, the match line devices of a row being connected in cascade, so that if a match is obtained along a row a current path is provided along the row to a respective current sensing circuit to indicate the match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.