Method and apparatus for testing random access memory
US5469443A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1993 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Oct 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a defect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1. At the end of phase two, the data values stored in the memory are again compared to a list of reference data values to determine whether the memory contains a fault. In phase three, an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.