Digital phase lock loop for jitter filtering and frequency offset compensation
US5469478A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Jul 15, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop for producing an output signal based on an input signal which is subject to jitter and frequency offset. The output signal follows the center of the jitter on the input signal to produce a jitter-filtered signal which compensates for the frequency offset. The digital phase lock loop includes a phase detector, a pulse scaler counter, a phase error counter and a first digitally controlled oscillator. The phase detector detects a phase difference between the input signal and the output signal and outputs up or down pulses depending on the phase difference. The pulse scaler counter increments an up/down counter when an up pulse is received from the phase detector, and decrements the up/down counter when a down pulses is received from the phase detector. When the up/down counter overflow or underflows, a correction pulse is output. The phase error counter resets during every cycle of the input and output signals. The phase error counter will increment an up counter when an up or down pulse is received from the phase detector. When the up counter overflows, a correction pulse is output. The first digitally controlled oscillator produces and outputs the output si…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.