Method and apparatus for refreshing a selected portion of a dynamic random access memory
US5469559A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1993 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Jul 6, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer. A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ranges of the DRAM that do not contain valid data, thereby conserving energy required to refresh the entire DRAM. The controller includes logic circuitry connected between a refresh period timer and the RAM device for inhibiting receipt by a RAS generator of a refresh pulse when a generated refresh address falls within the refresh address range defined by the region descriptor. A refresh address output by a refresh address counter compared to the region descriptors in the RAM device, and if the region descriptors indicate that the row addressed by the refresh address does not contain valid data, the RAS generator is inhibited from producing a RAS pulse. Logic instructions are inserted into memory allocation and memory deallocation subroutines of the computer's operating system for writing the region descriptors to the RAM device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.