Flexible parity generation circuit for intermittently generating a parity for a plurality of data channels in a redundant array of storage units
US5469566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1995 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Mar 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.