Operating system architecture using multiple priority light weight kernel task based interrupt handling
US5469571A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 1991 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | Jul 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A software architecture is implemented through the execution of instructions by a processor. The software architecture provides a first task for performing a first function in response to the occurrence of an interrupt. The first task is assigned a first priority level that is one of a predetermined set of priority levels. A server task is provided to perform a second function in response to the occurrence of the interrupt. The server task is assigned a second priority level that is between predetermined ones of the priority levels of the predetermined set of priority levels. The second priority level is alternately set higher than the first priority level. The operating system kernel includes a scheduler that selects tasks for execution based on relative task priority level. The kernel includes an interrupt handler that provides for setting the server task in a schedulable state in response to the occurrence of the interrupt. The server task, in performance of the second function, provides for setting the first task in a schedulable state with respect to the kernel scheduler so as to allow performance of the first function with respect to the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.