Providing alternate bus master with multiple cycles of bursting access to local bus in a dual bus system including a processor local bus and a device communications bus
US5469577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 1994 |
| Grant date | Nov 21, 1995 |
| Priority date | — |
| Expiry date | May 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system--including a processor, a local bus, local bus controls, and a memory subsystem--are contained in a single system unit (e.g. a card); (2) devices are coupled to the system unit and to each other through a device communications bus that is also accessible to the processor of the system unit; (3) the system processor is required to have principal access to the local bus, as a "System Bus Master", for time critical functions such as memory refresh; and (4) the devices include one or more devices that are required to have controlling access to the resources of the system unit, and for that purpose are required to have controlling access to the local bus as Alternate Bus Master entities. The disclosed arrangement allows an Alternate Bus Master operating in a burst mode, in which several cycles of data transfer may occur consecutively, to have continuous access to the local bus after a single signal handshaking exchange with the local bus controls; subject to over-riding conditions which ensure timely accomplishment of the time critical functio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.