High-speed large output amplitude voltage level shifting circuit
US5471149A · kind A · utility
3Cited by
7References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 6, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Sep 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level shifting circuit which enables realization of high sensitivity input, high speed, and large output amplitude with a low power consumption, wherein a flipflop is constituted by two CMOS inverters, INV.sub.1 and INV.sub.2, the power voltage sides of the CMOS inverters are used as the inputs of the signals, transfer gates are connected between the input terminals of the input signals and the input terminals of the CMOS inverters, and the transfer gates are turned on and off by the same clock signal CLK.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.