Interpolation filter with reduced set of filter coefficients
US5471411A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Apr 28, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0628
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.