Test circuit for refresh counter of clock synchronous type semiconductor memory device
US5471430A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | May 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.