Stack read/write counter through checking
US5471487A · kind A · utility
6Cited by
8References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 1994 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Apr 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for efficiently detecting an error on a memory stack write pointer or a memory stack read pointer by continuously monitoring the relative position between the two pointers. Using this technique, the present invention may detect certain classes of errors that cannot be detected by other error detection methods such as redundancy. The present invention eliminates the need to provide full redundancy thereby potentially saving considerable cost, size and power in a typical computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.