Address generating circuit using a base pointer of loop area
US5471600A · kind A · utility
25Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1995 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Feb 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2101/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generating circuit includes a latch circuit and two adder/subtractors. The inputs of the first adder/subtractor are from the latch circuit and from a distance relative to a value of a base pointer, and the output computes an address. The second adder/subtractor uses loop width information to adjust the computed address of the first adder/subtractor so that it falls within a loop area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.