Dynamically programmable timer-counter having enable mode for timer data load and monitoring circuit to allow enable mode only upon time-out
US5471608A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1993 |
| Grant date | Nov 28, 1995 |
| Priority date | — |
| Expiry date | Dec 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F1/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A programmable timer circuit is comprised of a programmable timer counter for receiving a count and for counting to the count. A clock signal for driving the timer counter which timer counter generates a signal representative of the count. A microprocessor generates count data in response to programming of the microprocessor. Timer data register receive the count from microprocessor. A first gate is provided having an enabled mode and an non-enabled mode for enabling loading of the timer data from the timer data register to the timer counter input only in the enabled mode. A monitoring circuit is provided for monitoring the timer count and enabling the gate mean to the enabled mode only when the timer has time-out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.