Method and circuit arrangement for measuring the depletion layer temperature of a GTO thyristor
US5473260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Jul 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01K7/01
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and a circuit arrangement having a device for measuring the depletion layer temperature of a GTO are specified. In this case, a measurement current (I.sub.M) is impressed in the gate circuit, and the voltage (U.sub.GR) between the cathode and gate is measured, with an applied measurement current (I.sub.M), after the transient turn-off processes have decayed. This voltage (U.sub.GR) is at this time dependent on the depletion layer temperature of the GTO. It thus becomes possible to measure the depletion layer temperature directly on the element, that is to say without circuitous routes via a heat sink temperature and calculation of the thermal resistance or the like, and during operation, continuously, and in consequence to monitor and control the stress level on the GTO precisely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.