Clock correction in a video data decoder using video synchronization signals
US5473385A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1994 |
| Grant date | Dec 5, 1995 |
| Priority date | — |
| Expiry date | Jun 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4341
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.